Multi-Level Cell (MLC) flash memory are useful for storing more than one bit of data on each memory cell. The writing of data into an MLC flash memory is typically slower than the writing of data into a Single-Level Cell (SLC) flash memory that stores only one bit of data per cell. Therefore, flash devices based on an MLC flash memory might not be capable of recording a stream of incoming data transmitted to it at a rate that exceeds the writing rate associated with the MLC flash memory.
Typically in cases where data is produced at a rate too high to be directly stored, a cache memory mechanism is provided and designed to operate fast enough to handle the incoming data stream. The cache memory utilizing a second (and faster) memory is implemented between the input data source and the main (and slower) memory of the flash memory device. The input data stream is first written into the faster cache memory, and at a later stage is copied from this faster cache memory into the main memory. As the copying operation between the cache memory and the main memory is typically performed in the background, this operation does not have to meet the strict performance conditions imposed by the input data stream rate, and therefore the lower write performance of the main memory is no longer an obstacle.
One type of flash memory device is a ‘peripheral flash storage device” which is now discussed with reference to FIG. 1.
“Peripheral flash storage devices” 260 are well-known in the art of computing, in form factors such as USB flash drives (UFD); PC-cards; and small storage cards used with digital cameras, music players, handheld and palmtop computers, cellular telephones or any other form factor.
When coupled to a host device 310 (for example, a laptop or desktop computer or a mobile telephone), the peripheral flash storage devices 260 may receive user data via respective host side 350 and device side 250 interfaces (for example, a USB interface or an SD interface or an MMC interface or any other kind of wired or wireless interface). The received data may be written by flash controller 280 to flash memory 270 of the flash memory storage device.
Although host 310 and flash 260 devices are illustrated in FIG. 1 as separate devices, it is understood that in some embodiments, flash device 260 may be deployed within a housing of host device. Alternatively, flash device 260 may be deployed outside of a housing of host device.
As illustrated in FIG. 1, host device 310 sends data to flash memory storage device 260 (for example, associated with a write command). The data, which is received from the host, is written to volatile memory 282, for example by flash controller 280. Although volatile memory 282 is depicted in FIG. 1 as separate from flash controller 280, it is appreciated that, in some embodiments, volatile memory 282 (for example, RAM) may reside within and/or be a part of flash controller 280,
After the data is written to volatile memory 282, it is copied to flash memory 270.
It is noted that when the host device 310 sends a write command to the flash device 260, there may be a need for the flash device 260 to write the data to flash memory 270 as soon as possible in. On the other hand, as noted above, sometimes other design considerations (e.g. the need to greater device capacity and/or reliability) may require that a “slower” writing mode that is slower than the fastest possible writing mode be used.
Towards this end, as illustrated in FIG. 2A, it is common in flash devices for flash memory 270 to include both a cache storage area 272 and a main storage area 274 for “longer term” storage. Incoming data may, at least some of the time, be written to the cache storage area 272 and, at a later time, be copied from cache storage area 272 to the main storage area 274.
In different implementations, the cache storage area 272 is written to using a ‘faster writing mode’ that is faster than a writing mode used for main storage area 274 and/or the main storage area 274 is larger (i.e. has a greater capacity) than the cache storage area 272.
In one particular example, cache storage area 272 includes flash blocks where K bits of data are stored in each flash cell where K is a positive integer, and the main storage area 274 includes flash blocks where L bits of data are stored in each flash cell where L is a positive integer that exceeds K.
FIG. 2B relates to a first use case. According to this use case, data is written to the cache storage area only.
In the example of FIG. 2C, which relates to a second use case (i) data is first written to the cache storage area 272; and (ii) at a later time, the data is copied from the cache storage area 272 to the main storage area 274.
The example of FIG. 2D, relating to a third use case, describes “cache bypassing.” In this third use case, data is written directly to the main storage area 274 without first being written to the cache storage area 272.
FIG. 3 is a flow chart describing a technique for storing data to a flash memory 270. In step S211, the peripheral storage device 260 receives data from host device 310. In step S215, this data is stored in volatile memory (for example within flash controller 280 or at any other location within non-volatile memory device 260).
As illustrated in the use cases described with reference to FIGS. 2B-2D, the data is either (i) written to cache storage area 272 before being written (if written) to main storage area 274 (use cases 1 and 2)—i.e. the ‘first flash writing’ of the data is to cache 272 or (ii) is written to main storage area 274 without being written to cache storage area 272 (use case 3)—i.e. the ‘first flash writing’ of the data is to the main storage area 274.
For the former case (use cases 1 and 2), the ‘yes’ branch leaving step S219 is selected, and the data is written (in step S223) into the cache storage area 272. Optionally (see use case 2) and typically with a ‘high frequency’ or an ‘extremely high frequency,’ the data is copied (see the optionally line leaving the box of step S223) from the typically smaller cache storage area to the larger main storage area for longer-term storage. Copying the data allows the region within cache 272 in which the data was stored to be used to store new data
For the latter case (use case 3) relating to ‘bypassing’ the cache, the data may be written directly to main storage area 274 (according to the ‘no’ branch leaving step S219) without writing the data first to the cache storage area
Referring back to FIG. 1, it is noted that flash controller 280 may be implemented using any combination of hardware (for example, including a microprocessor and optionally volatile memory such as RAM or registers), firmware and/or code-modules (for example, stored in volatile and/or non-volatile memory and executable by a microprocessor). Flash controller 280 may include any software (i.e. tangibly stored in volatile and/or non-volatile memory) and/or firmware and/or hardware element(s) including but not limited to field programmable logic array (FPLA) element(s), field programmable gate array (FPGA) element(s), and application-specific integrated circuit (ASIC) element(s). Any instruction set architecture may be used in flash controller 280 including but not limited to reduced instruction set computer (RISC) element(s) and/or complex instruction set computer (CISC).
There is an ongoing need for method and apparatus for storing data to non-volatile memories including a cache storage area and a main storage area.